1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a test structure for testing the accuracy of formation of conductive structures using both visual and electronic inspection techniques.
2. Description of the Relevant Art
High yields are essential to the profitable manufacture of integrated circuits. Yield prediction, used to estimate the manufacturing yield of a new integrated circuit, is accordingly a very valuable tool in assuring that such manufacture will be economically successful.
A wafer fabrication process typically forms multiple integrated circuits upon each of several silicon wafers processed simultaneously. As the integrated circuits formed on a given silicon wafer are identical copies of a given product, the silicon wafer is sometimes referred to as a product wafer. An individual integrated circuit is also called a "chip" or a "die". Following wafer fabrication, the die are subjected to functional testing, then separated. Fully functional die are typically packaged and sold as individual units.
In general, the yield associated with a product wafer manufactured using a particular wafer fabrication process depends upon: 1) the number of steps in the wafer fabrication process, 2) the number of defects introduced during each processing step, and 3) the vulnerability of the features formed during a given processing step to the defects introduced during the processing step.
A defect is simply a flaw caused by an imperfect manufacturing process. Only some of the defects associated with a given step are "full" defects, or defects which prevent an integrated circuit containing the defect from performing its intended function. It is well known that most defects occur during microstructure patterning steps. Photolithography is used to accomplish such patterning steps, during which light passing through a pattern on a mask transfers the pattern to a layer of a light-sensitive material deposited on the surface of a silicon wafer. The layer of the light-sensitive material is developed in a manner analogous to the developing of exposed photographic film. Exposure to light makes certain regions of the layer of light-sensitive material soluble. The developing step removes the soluble regions, forming holes in the layer of light-sensitive material. Select regions of the upper surface of the silicon wafer are exposed to an etchant or to dopant atoms through the holes during a subsequent processing step. Small particles (i.e., particulates) on the surface of the mask or on the surface of the photoresist layer, which block or diffuse light, cause imperfect pattern registrations (i.e., imperfect feature formations). Particulates may be present in the ambient air, introduced by processing personnel, suspended in liquids and gases used during processing, or generated by processing equipment. In general, the vulnerability of a particular feature to a given defect is inversely proportional to the physical dimensions of the feature. Thus the smaller the physical dimensions of a feature formed using photolithography, the greater the likelihood that a particulate of a given size will cause a full defect.
There are two basic types of defects which may occur when conductive layers are formed on an integrated circuit topography. Extra material defects ("EMDs") may occur when the conductive structures include material extending beyond the predefined boundaries. Such material may extend to another conductive structure causing a "short" to be formed between the two conductive structures. Missing material defects ("MMDs") may occur when a conductive structure is formed which is missing some of its conductive material. Such a defect may cause the formation of an "open" conductive structure in which the continuity of a conductive structure is broken.
EMDs and MMDs may be detected using test structures. Typically, these test structures include a number of electrically testable conductive lines. Electrical probing of these conductive lines may be used to determine the presence of shorts between two or more conductive lines or the presence of opens in a conductive line. FIG. 1A depicts a typical test structure used to test for EMDs. The test structure includes a first conductive comb 10 with a test pad 12 and a second conductive comb 20 with a test pad 22. The combs are formed in close proximity to each other. If no EMDs are present, electrical probing of pads 12 and 22 will show no electrical connection (e.g., high resistance). If, however, a conductive EMD 30 having a sufficient size to bridge at least two of the conductive lines is present, as depicted in FIG. 1B, a short may be formed between the two conductive lines, thus allowing an electrical connection to be formed. When pads 12 and 22 are simultaneously probed, an electrical connection (e.g., a low resistance) may be detected.
FIG. 2A depicts a serpentine structure which may be used to test for MMDs in a conductive structure. The test structure includes a serpentine conductive line 40 with test pads 42 and 44 formed at both ends of the line. If no MMDs are present, electrical probing of pads 42 and 44 should show conductivity between the two pads. If, however, an MMD 50 is present, as depicted in FIG. 2B, sufficient material may be absent such that the connectivity of the conductive line is broken. This MMD may be detected when electrical probing of the pads reveals a decrease in conductivity between the pads.
A disadvantage of these types of test structures is that every line has to be individually probed to check for these defects. If a large number of test structures are present, the electrical testing of each of these test structures may take an undesirable length of time. It would be desirable to develop a test structure and method which can more rapidly determine the presence of defects. Such a structure and method would be beneficial in rapidly detecting the presence of unacceptable defects during a production run.
Another disadvantage of a conventional test structure is that the tolerance of the test structure with respect to partial defects may be difficult to assess. The above described test structure may be used to determine the presence of full or "absolute" defects which cause a complete open or short of a conductor within the test structure. However, the cause of such defects may be harder to determine. For example, EMDs are typically determined when a short is detected between adjacent conductive lines. When such a defect is found, it may be difficult to determine the dimensions of the particle which caused the defect to occur. As described above, small particles on the surface of the mask or on the surface of the photoresist layer, which block or diffuse light, may cause imperfect pattern registrations (i.e., imperfect feature formations). However, the size of the defect may not correspond to what would be expected based on the size of the particle on the mask or photoresist layer. For example, a particle which bridges only 50% of the space between the conductive lines may, ultimately, cause a full defect, i.e., a defect that causes a short between the conductive lines. The initial defect may be "expanded" due to poor resolution in subsequent photoresist and conductive feature processing steps. Alternatively, the partially extended defects may expand over time through electromigration. Thus, the presence of defects in a test structure may be erroneously attributed to large particles, when, in fact, smaller particles are actually causing the problems. This may lead to difficulties in isolating and preventing the formation of such defects. For example, if it is determined that the particle causing a defect has an expected size, which is based on the size of the defect, and which is larger than the actual size of the particle, filtering techniques to remove such particles may be inadequate. It is therefore desirable that a more accurate method of determining the tolerance of conductive features toward partial defects be devised.
It is also desirable to have a test structure which may be used in a process to validate inspection tools. As described above, electrical testing can be a time consuming process. Other types of inspection, i.e., optical and voltage contrast inspections, may be performed more rapidly than electrical testing. However, such inspection techniques may not be able to detect smaller defects, which would be found by electrical testing techniques. It is therefore desirable to have a test structure designed for use in testing the ability of optical and/or voltage contrast inspection tools to find defects.